On-wafer parametric and Known Good Device (KGD) testing for high voltage devices can be challenging. Test voltages in excess of 600 V are typically applied to a wafer with semiconductor devices under test in order to measure leakage and/or breakdown voltage. Often high voltage ionization and breakdown of air or surface flashover will confound electrical measurements of the semiconductor devices' intrinsic device performance. For example, an electric field of around about 30 kV/cm will cause the air between features of a semiconductor device to ionize, which will usually allow a destructive energy flow into the semiconductor device. Fortunately, electric field levels for materials making up semiconductor devices typically exceed 30 kV/cm. Thus, high voltage semiconductor devices are packaged such that an ionization of air to the point of breakdown is prevented. However, before packaging and during wafer testing an air ionization leading to a destructive voltage breakdown is an ever present risk for the semiconductor devices under test. Moreover, even nondestructive voltage breakdowns resulting from air ionization and/or flashover are not indicative of intrinsic device performance.
A common technique for suppressing air ionization and breakdown is to dispense a fluid having a relatively high dielectric strength onto a wafer having semiconductors to be tested. Examples of high dielectric strength fluids include fluorocarbon-based fluids such as perfluorohexane (C6F14). While suppressing air ionization and breakdown using high dielectric strength fluids is effective, it is also impractical for high volume production testing.
FIG. 1 depicts a cross-section of a prior art semiconductor device 10 before undergoing a prior art approach that involves depositing a relatively increased amount of a high dielectric strength material that makes up a passivation layer 12, that at least partially covers conductive features 14 and 16 to suppress air ionization. The semiconductor device 10 has a substrate 18 that carries epitaxial layers 20 onto which the conductive features 14 and 16 are disposed. The passivation layer 12 also covers a section of the epitaxial layers 20 that is between the conductive features 14 and 16.
High electric fields between the conductive features 14 and 16 can sometimes be confined to the passivation layer 12. However, a destructive breakdown may still occur if the layer thickness of the passivation layer 12 is not thick enough. In such a case, a thickening of the passivation layer 12 may be considered as illustrated in FIG. 2. However, there are practical limitations as to how thick the passivation layer 12 can be. For example, inorganic dielectrics like silicon nitride (SiN) are more prone to cracking as a function of increased thickness. A practical thickness for SiN is around about 1 μm, whereas a thickness approaching 5 μm is approaching impracticability. Moreover, if the passivation layer 12 is deposited using a relatively slow process such as atomic layer deposition (ALD), impracticalities of excessive time consumption and excessive cost are introduced for the deposition of material layers greater than 0.1 μm. Thus, a need remains for a high voltage on-wafer testing method for semiconductor devices in a high volume production environment.